1. Field of the Invention
The present invention relates to a method of transferring data by a direct memory access (DMA) controller.
2. Description of the Related Art
DMA transfer has been well known as a technology for reducing the offload on a CPU when data is read from memory. As disclosed in unexamined patent publication No. 2003-198817, in DMA transfer, a DMA controller reads desired data using a descriptor which is memory area management information. In the patent document, image data is read from a specific area of image memory based on the descriptor taken out from the memory with reference to the storage area of data. By dividing transfer units of data using the descriptor of the DMA controller and implementing data transfer in time division, data transfer can be made to operate as if a plurality of data transfer were being implemented in parallel.
FIG. 10 shows the sequence of the conventional processing in which the DMA controller reads the data designated by the descriptor. For example, when an instruction directing that desired data should be read is inputted from another device such as a keyboard and a mouse, firstly, the DMA controller 4 reads the descriptor. Next, the DMA controller 4 reads the data from the memory area designated by the descriptor. Then, the read data is transferred to a device of the transfer destination.
Numbers in parentheses shown in FIG. 10 indicate the order for implementing DMA transfer processing. Described below is the DMA transfer processing related to the prior art in the order of the numbers shown in the figure.
<1> The CPU 2 instructs the DMA controller 4 to read the descriptor stored in the memory 3.
<2> The DMA controller 4 requests the memory controller 5 to read the descriptor.
<3> The DMA controller 4 receives the descriptor read from the memory 3 via the memory controller 5.
<4> The DMA controller 4 requests the memory controller 5 to read the data stored in the area designated by the received descriptor in the memory 3. The memory controller 5 implements advance-preparation processing and processing of waiting for the assignment of the right to use buses during a period from the time when the memory controller 5 receives a request for data reading from the DMA controller 4 to the time when the memory controller 5 transmits the request for data reading to the memory 3, namely before the memory controller 5 actually implements the processing of reading the data from the memory 3. When the right to use a bus is assigned, the memory controller 5 proceeds to the processing of <5>.
<5> The memory controller 5 begins to read the data from the memory 3.
<6> The data is read from the memory 3 based on the descriptor. The data read from the memory 3 is transferred to the memory controller 5 via the data bus 7, and the data is stored in the pre-fetch buffer in the memory controller 5.
<7> The memory controller 5 successively transfers the data stored in the pre-fetch buffer to the DMA controller 4. When the processing speed for storing data in the pre-fetch buffer is compared with the processing speed for transferring the data in the pre-fetch buffer to the DMA controller 4, generally the speed required for the transfer processing is slower. Consequently, the data acquired from the memory 3 is gradually accumulated in the pre-fetch buffer. Thus, when the amount of data in the pre-fetch buffer exceeds a prescribed value, the memory controller 5 releases the request once for data reading from the memory 3 corresponding to the descriptor. That is to say, the memory controller 5 releases the data bus 7.
<8> The memory controller 5 continuously implements advance-preparation processing for reading the data which has not been transferred from the memory 3, and requests the use of buses for obtaining the right to use the control bus 6 and data bus 7 again.
<9> After obtaining the right to use the control bus 6 and the data bus 7, the memory controller 5 reads the data which has not been transferred from the memory 3 and successively transfers the data to the DMA controller 4 via the data bus 7.
After then, the same processing as <5> through <8> is repeated until all the data which the DMA controller 4 requests is read from the memory 3.
<10> When the transfer to the DMA controller 4 of data equivalent to the amount of data which the DMA controller 4 requests is completed, the DMA controller 4 transmits a notification of the completion of transfer to DMA to the CPU 2 and terminates the processing. The data read from the memory 3 is transferred to a prescribed device from the DMA controller 4.
In the conventional DMA transfer method, when reading of data corresponding to one descriptor from the memory 3 is implemented two times or more, it is necessary to implement advance-preparation processing and wait until the right to use the buses is assigned each time, as shown in FIG. 10. Here, while the memory controller 5 is implementing the advance-preparation processing and is waiting for the right to use the buses, the data bus 7 is not used. In other words, in the conventional technology, the period in which the data bus 7 is not used arises each time a prescribed amount of data is read from the memory 3 and is transferred to the memory controller 5.
Each time the memory controller 5 requests that the data which has not been transferred should be read from the memory 3, it is necessary to implement the advance-preparation processing and the processing for obtaining the right to use the control bus 6 and the data bus 7. Consequently, each time data equivalent to a prescribed amount of data is taken out from the memory 3 to the pre-fetch buffer in the memory controller 5, a period in which the data bus 7 is not used for data transfer due to memory latency arises. From the viewpoint of improving the use efficiency of the buses, namely, throughput in DMA transfer, it is preferable to shorten the period in which the data bus 7 is not used.